Buck converters, including both single-phase and multi-phase buck converters, are widely used in high power applications because of their high efficiency and small amount of area/volume required for implementation. High performance integrated circuits such as microprocessors, graphics processors, network processors, high speed memories, etc. require high current at low voltage. In computing applications, buck converters drive high output capacitance loads such as memory banks like DIMMs (dual in-line memory modules) and/or face very large stringent startup constraints. For example, the output voltage may be regulated to a tight voltage tolerance so as to optimize operation of one or more memory banks. The output load and output capacitance supported by a buck converter often are quite variable. Again in the case of memory banks as the load, the output capacitance depends on whether the memory bank sockets, e.g. typically ranging from 1 to 12 sockets, are populated or unpopulated. The output power therefore can be quite variable depending on system loading, so that the input power available may be heavily constrained, and its capability may be easily exceeded.
During the start-up period of a buck converter, high output capacitance results in a very slow response system. Standard fast compensation schemes issue larger PWM (pulse width modulation) pulses for delivering more current to charge the high output capacitance. This is seen as an “in-rush” current. The larger the output capacitance, the larger the in-rush current. Eventually, the voltage across the output capacitance reaches a soft-start reference voltage. A degree of overshoot may be observed due to the output inductor(s) of the buck converter continuing to charge the output capacitance, even though there is an absence of PWM activity. That is, the in-rush current surges into the system and causes the output voltage to rise at a faster rate than programmed and therefore the output voltage does not rise from 0V to the final set-point voltage at a constant rate. A large amount of inrush current also increases the risk of triggering system shutdown due to overcurrent protection.
One typical solution for reducing the impact of inrush current and for resolve overcurrent protection faults during buck converter start-up is to reduce the (slew) rate at which the target voltage increases. This approach provides a slower moving reference for the output voltage to track, requiring less output current. The reduction in slew-rate slightly reduces the peak required, but the inrush current is still present. Moreover, a reduced slew-rate principally affects the steady-state current required to charge the output capacitance and not the initial start-up period. In another approach, a hard limit is set on the amount of peak-current the control system allows through the switching power-stage. However, this approach requires a very low peak-current limit which impedes voltage regulation during normal transient conditions. Also, the system has a poor recovery/response once the output voltage reaches the target level. Still other approaches involve increasing or over-designing power system capability which presents inefficiencies during regular operation, and/or limiting the number of memory modules or output capacitance which restricts the end application.
As such, there is a need for improved inrush current limiting techniques during startup of buck converters.